Marqs has revealed the successor to his Open-Source Scan Converter (OSSC), a zero lag scaler for 240p to 480p analog video, than can double or even 5x scale sources to HDMI & DVI. Dubbed the OSSC Pro, it will be built around a much more powerful Cyclone V FPGA heart, the same series used in Analogue products and MiSTer, although each use a different Cyclone V model.
I spoke with Marqs at RetroCreate—a meetup of creators hosted by RetroRGB—in November, and he mentioned a major secret project that he had been working on for some time already, and the OSSC Pro would appear to be it.
The Pro aims to improve every aspect of the original OSSC, while adding a host of new features. The most interesting of which, to me, is screen rotation, which will be useful for vertical/TATE orientation arcade games.
Marqs posted concept pictures, a block diagram, and a list of the intended new features. He even has hardware add-on PCBs planned that will allow tinkerers to upgrade popular FPGA dev kits like the DE10-Nano, for those who can’t wait for the final product.
For more details and to join the discussion, head over to the forum thread where the Pro was revealed.
Highlights of the new design:
ISL51002 video ADC:
* improved sync processing robustness
* reduced sampling jitter with DPLL
* fine-grained video LPF
* automatic sampling phase adjustment
Cyclone V FPGA (5CEFA5F23C8N):
* higher performance and more resources
* hard memory controller
* large number of IOs
Clocking and memory improvements:
* Si5351C clock generator for accurate output pixel clock generation (framelock or free-running)
* 512MB LPDDR2 RAM and 16MB QSPI flash
New AV inputs:
* SPDIF (optical)
2×20 pin GPIO connector for future expansion possibilities such as:
* composite & s-video input module
* secondary video output (e.g. VGA) module
* latency tester interface module
* game controller port module (for using OSSC Pro as a dedicated FPGA console)
The processing modes enabled by the HW can be split roughly into three types:
1. Pure line multiplier
* both active and blanking lines multiplied – basically what original OSSC does
* simplest mode with least latency
2. Adaptive line multiplier
* visible lines are multiplied but horizontal & vertical total matched to standard timings
* high compatibility with minimal latency overhead (1-30 lines typically)
* enables some new output configurations such as 4x240p/2x480p in standard 1080p frame
* higher flexibility via LPDDR2 utilization
* HQ deinterlacing
* non-integer scaling
* refresh rate conversion
It will take time until all the features get implemented, but release can be expected once the HW is complete and a sufficient number of new features are available and verified. As a thanks to community’s support for the first project, upcoming prototypes of the new model will be sent to the guys who have contributed most on the original OSSC firmware. New developers are also welcome as the project is large enough to enable different implementation areas for several people. For DIY-builders and those who can’t wait for the final HW, a small add-on PCB compatible with a couple Terasic FPGA dev boards (DE10-Nano, DE2-115) is in works and available soon. Together with the parent dev board, it can be used to implement a subset of the functionality presented above.
UPDATE: Video Game Perfection has some more official information about it, as well as announced that the original OSSC will both continue to be sold and have the price lowered to around $120!!!: https://videogameperfection.com/2020/01/18/ossc-pro-is-coming/
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